The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling down has also increased the complexity of processing and manufacturing ICs. For these technological advancements to be realized, similar developments in IC processing and manufacturing are needed.
For example, multi-gate devices have been introduced in an effort to improve gate control by increasing gate-channel coupling, reduce OFF-state current, and reduce short-channel effects (SCEs). One type of the multi-gate devices is FinFETs—transistors with a fin-like semiconductor channel (“fin”) and a gate electrode engaging the fin on two or three sides thereof. In a typical FinFET formation process, fins are formed out of a substrate (e.g., through epitaxial and/or etching processes) and are separated by deep trenches. The trenches are subsequently filled with a gap-fill dielectric material as an isolation structure. As the device miniaturization continues, the aspect ratio (height vs. width) of the trenches also increases. As a result, the density of the gap-fill material is decreased in order to fill the deep trenches properly. However, the low density gap-fill material frequently suffers from scratch defects during subsequent chemical mechanical planarization (CMP) processes. Furthermore, a single layer of the gap-fill material is sometimes inadequate to meet low wet etch rate requirements. In these cases, two or more layers of gap-fill materials are deposited as a film stack. Adjacent films in the film stack sometimes suffer from poor adhesion between them.
Accordingly, improvements in these areas are desired.